Why is UVM the Universal Verification Methodology?
The Universal Verification Methodology, UVM, is a standard being developed by Accellera for the expressed purpose of fostering universal verification IP interoperability. Led by electronics companies and supported by a suite of companies representing the breadth of the verification ecosystem, the UVM will increase productivity by eliminating expensive interfacing that slows verification IP reuse.
UVM Overview Graphic
Background
As the verification challenge has grown during the past decade, several solutions emerged to address both complexity and reuse. Each one had its own value and niche resulting in project success but also leading to divergence in the verification ecosystem. In January 2008 the OVM, Open Verification Methodology, emerged and helped usher a convergence around two main solutions VMM and OVM. Accellera created the Verification IP Technical Subcommittee (VIP TSC) in February 2008 to first work on interoperability between these two solutions and then to address a single solution. Accellera achieved the first milestone in July 2009 with the release of the Interoperability Best Practices and reference library. The UVM 1.0 EA is the first delivery of the second milestone.
UVM 1.0 EA is based on the OVM 2.1.1 release and incorporates some incremental functionality to validate the SourceForge-based development process. The incremental functionality comes from a collaboration of VMM, OVM, and new technology developed by the Accellera VIP TSC. Along with the base-class library (BCL), the UVM 1.0 EA provides two important documents – a reference manual to the APIs in UVM and a user guide suggesting how to apply UVM – both of which originated with the OVM but are updated to UVM. Accellera members have tested the UVM 1.0 EA is on multiple simulators to enable the verification IP developed with it to run universally.
The UVM 1.0 EA achieved something many people doubted could be done: release the UVM in any form. Even those who thought UVM was possible believed it would devolve into the lowest common denominator, but the reality of UVM 1.0 EA refutes that notion. The Accellera VIP should be congratulated for proving that true industry collaboration is not only achievable but can build remarkable technology. With EA we are just starting on a path that will raise productivity throughout the verification ecosystem.
Key Benefits
Eliminates need for interoperability among verification libraries
Based on a BCL proven in 1000s of projects
Incorporates the collective verification knowledge of the Accellera members
Written in IEEE 1800 SystemVerilog
Runs on any simulator supporting the IEEE 1800 standard
True open-source license agreement (Apache 2.0)
New Features in UVM 1.0 EA
Callbacks and end-of-test from OVM extended
To enable registration by type simplifying the coding of callbacks
With a new API to support a report catcher to demote specific messages based on user-defined criteria
With a new callback to enable the end-of-test mechanism to identify when a component raise or drops an objection
With new callbacks for raised, dropped, all_dropped
A heartbeat mechanism to provide a central watchdog feature
Welcome to UVM World!
May 17th, 2010
The first release of UVM is now available from the Accellera VIP Technical Sub-Committee. Many people have questioned whether it would be possible to build a standard SystemVerilog verification base class library and methodology, but with the UVM 1.0 EA release, this question has been clearly answered. The Accellera VIP TSC should be congratulated for proving that true industry collaboration is not only achievable but can also enable the delivery of remarkable technology. With the EA release, we are just starting on a path that will raise productivity throughout the verification ecosystem.
To that end, we here at the UVM World Community Site welcome you to the industry-open www.uvmworld.org. Many of us have seen that a lot of the momentum that OVM has today comes from the power the ecosystem brings through the OVMWorld.org site and we are driven to have that power replicated for the UVM community.
UVM World will be open to contributions, blogs, entries to forums, and so forth. It will not be the repository for the UVM code and documentation, but will provide links to the official Accellera repository site in order to provide easy access to UVM releases for those interested.
One thing you will notice as you browse UVM World is that this is not a Cadence-branded site. Rather, in the spirit of other open sites such as OVMWorld.org, VMMCentral.org and SystemVerilog.org that were funded by EDA vendors but were unbranded, UVMWorld.org is being established by Cadence to develop an open community—the UVM community.
Welcome!
Stan Krolikoski
Cadence Design Systems
UVM Overview
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